ARMv8 has many versions (ARMv8.1, etc), which define mandatory and optional features. The Linux kernel exposes the presence of some of these features via hwcaps. These values are displayed in /proc/cpuinfo.
So if you "grep Features /proc/cpuinfo", you may get a result like:
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics cpuid asimdrdm
This table shows the feature name, what version introduced the feature, and a short description.
| Name | Versions | Feature Supported |
|---|---|---|
| fp | ARMv8.0 | Single-precision and double-precision floating point. |
| asimd | ARMv8.0 | Advanced SIMD. |
| evtstrm | N/A | Generic timer is configured to generate "events" at frequency of about 100KHz. |
| aes | ARMv8.0 | AES instructions (AESE, etc) |
| pmull | ARMv8.0 | Polynomial Multiply Long instructions (PMULL/PMULL2) |
| sha1 | ARMv8.0 | SHA-1 instructions (SHA1C, etc) |
| sha2 | ARMv8.0 | SHA-2 instructions (SHA256H, etc) |
| crc32 | [ARMv8.0], ARMv8.1 ... | CRC32/CRC32C instructions |
| atomics | ARMv8.1 ... | Large System Extensions (LSE) - (CAS/SWP/LD[op]) |
| fphp | ARMv8.2-FP16 | Half-precision floating point. |
| cpuid | N/A | Some CPU ID registers readable at user-level. |
| asimdrdm | ARMv8.1 | Rounding Double Multiply Accumulate/Subtract (SQRDMLAH/SQRDMLSH) |
| jscvt | ARMv8.3 | Javascript-style double->int convert (FJCVTZS) |
| lrcpc | ARMv8.3 | Weaker release consistency (LDAPR, etc) |
| dcpop | ARMv8.2 | Data cache clean to Point of Persistence (DC CVAP) |
| sha3 | ARMv8.2-SHA | SHA-3 instructions (EOR3, RAXI, XAR, BCAX) |
| sm3 | ARMv8.2-SM | SM3 instructions |
| sm4 | ARMv8.2-SM | SM4 instructions |
| asimddp | ARMv8.2-DotProd | SIMD Dot Product |
| sha512 | ARMv8.2-SHA | SHA512 instructions |
| sve | ARMv8.2-SVE | Scalable Vector Extension (SVE) |
This should be complete up until ARMv8.4 features (ran out of time).
See kernel docs and the ARMv8-A Reference Manual for (way) more details...